How to Increase Sampling Rate on ChipWhisperer-Husky for Higher ADC Samples per Trace

1

I’m trying to increase the sampling rate on my ChipWhisperer-Husky for power analysis on a CW305 target (AES). Using scope.clock.adc_mul = 12 with scope.clock.clkgen_freq = 7.37e6 gives the following errors:

(ChipWhisperer Scope WARNING|File ChipWhispererHuskyClock.py:663)

Could not calculate pll settings for the requested frequency (7363636); generating a 7333333 clock instead. It may be possible to get closer to the requested frequency with a different adc_mul. It may also be possible to get closer to the requested frequency if you set scope.clock.pll._allow_rdiv to True; however this can result in an inconsistent clock phase between the target and ADC clocks; use at your own risk!

(ChipWhisperer Scope WARNING|File ChipWhispererHuskyClock.py:703) Target clock may drop; you may need to reset your target.

Target connection test passed

Current Setup:

  • ADC Samples: 60 (scope.adc.samples = 60)

  • Clock: scope.clock.clkgen_freq = 7.37e6, scope.clock.adc_mul = 12 (~88.44 MS/s expected)

  • Code:

    scope = cw.scope()

    scope.clock.clkgen_freq = 7.37e6

    scope.clock.adc_mul = 12

    scope.adc.samples = 60

    scope.adc.stream_mode = False

    trace = cw.capture_trace(scope, target, bytearray(16), bytearray(16))

Goal: Achieve a stable sampling rate >60 MS/s (e.g., 80–100 MS/s) for finer-grained power traces.

Questions:

  1. How can I resolve the PLL error to achieve a stable 88.44 MS/s or higher with adc_mul = 12?

  2. Is setting scope.clock.pll._allow_rdiv = True safe for power analysis, given the clock phase warning?

  3. What’s the maximum stable clkgen_freq and adc_mul for Husky?

Any advice on optimizing clkgen_freq, adc_mul, or other parameters to achieve a stable, high sampling rate would be greatly appreciated!

2

How can I resolve the PLL error to achieve a stable 88.44 MS/s or higher with adc_mul = 12?

I just want to note that this isn’t an error, just a warning about what clock frequencies you can generate. As the warning states, the PLL cannot generate two phase locked clocks with a 12x frequency difference at 7.37MHz. The closest it can get is 7.33MHz, which may or may not be acceptable, which is why it warns you. There’s no issue with clock stability or anything like that.

I’d have to check with @jpthibault since he was the one who identified this, but I believe this specifically refers to a stable phase when using an external clock.

The max sampling frequency is 200MS/s. I think technically the limit we have on the clkgen_freq is 300MHz, but obviously your ADC won’t work at this frequency. I don’t think there’s a limit on the adc_mul either (so long as you don’t go above 200MS/s on the ADC clock), but larger adc_mul values will have fewer clkgen_freq values.

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3

It is "safe” but as the message indicates, the phase between the target clock and the ADC sampling clock may be inconsistent, i.e. every time you run your script you could have a different phase between these two clocks. It’s up to you to determine if you’re ok with that. Personally I would avoid it.

If you go above 200 MS/s, Husky can misbehave – it could miss samples, it could fail to trigger, or any number of other “bad things”.

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