How to Modify Examples for my Own Design

1

Hello! I am a student from National Yang Ming Chiao Tung University, and I recently purchased your company’s CW305 Artix FPGA Target for conducting side-channel attack research. I have a few questions regarding modifying the provided examples for my own designs:

When working with your provided examples, what steps are needed to adapt them for my own design? For instance, how can I generate input signals for the design under test? How should I design the process to verify if the collected output from the design is correct?

Thank you!

2

Hi,

@jpthibault usually handles FPGA questions and is currently on vacation, so it might be a little bit before your question gets answered

3

The first step is to understand how our examples work, and it sounds like you’ve already done that.

Our CW305 appnote has a section “Porting your own AES Core” that you will find useful. It’s titled “AES” but it’s applicable to any target design; for example our ECC target uses the same interface and approach.