Hi,
I’m having some issues with trying to setup UART triggering on my Husky. I’ve got the UART coming in via Aux in/Out SMB.
Here is my setup:
import chipwhisperer as cw
scope = cw.scope(name="Husky")
scope.clock.clkgen_src = 'system'
scope.clock.clkgen_freq = 20e6
scope.clock.adc_mul = 2
scope.glitch.enabled = True
scope.glitch.clk_src = 'pll'
scope.clock.fpga_vco_freq = 600e6
scope.glitch.trigger_src = "ext_continuous"
scope.glitch.ext_offset = 0
scope.glitch.output = "enable_only"
scope.glitch.repeat = 10
scope.glitch.offset = 0
scope.io.glitch_lp = True
scope.io.glitch_hp = False
scope.UARTTrigger.enabled = True
scope.trigger.module = "UART"
scope.io.aux_io_mcx = 'high_z'
scope.trigger.triggers = 'aux'
scope.clock.reset_adc()
scope.UARTTrigger.clock.fe_clock_src = "usb_clock"
print(scope.UARTTrigger.clock.fe_clock_alive)
print("fe_freq: %f" % scope.UARTTrigger.clock.fe_freq)
scope.UARTTrigger.baud = 115200
print("fe_freq: %f" % scope.UARTTrigger.clock.fe_freq)
pattern = [x1A]
mask = [0xFF]
scope.UARTTrigger.set_pattern_match(0,pattern, mask)
scope.UARTTrigger.trigger_source = 0
scope.arm()
print("fe_freq: %f" % scope.UARTTrigger.clock.fe_freq)
print(scope.UARTTrigger)
Which always returns a “SWO clock not locked!” error.
True
fe_freq: 70756919.860840
(ChipWhisperer Scope WARNING|File TraceWhisperer.py:1414) Coudln't achieve exact desired frequency (141513839.721680); setting to 141644659.042358 instead.
(ChipWhisperer TraceWhisperer ERROR|File TraceWhisperer.py:2237) SWO clock not locked!
fe_freq: 82041023.254395
fe_freq: 82041023.254395
cwhusky Device
sn = ***
fpga_buildtime = 5/26/2026, 09:27
fw_version =
major = 1
minor = 7
debug = 0
gain =
mode = low
gain = 0
db = 15.0
adc =
state = False
basic_mode = rising_edge
timeout = 2
offset = 0
presamples = 0
samples = 131124
decimate = 1
trig_count = 0
stream_mode = False
test_mode = False
bits_per_sample = 12
segments = 1
segment_cycles = 0
segment_cycle_counter_en = False
clip_errors_disabled = False
lo_gain_errors_disabled = False
errors = False
clock =
clkgen_src = system
clkgen_freq = 20000000.0
adc_mul = 2
adc_freq = 40000000.0
adc_rate = 40000000.0
freq_ctr = 0
freq_ctr_src = extclk
clkgen_locked = True
adc_phase = 0.0
extclk_monitor_enabled = False
extclk_error = False
extclk_tolerance = 1144409.1796875
trigger =
sequencer_enabled = False
module = UART
triggers = sma
io =
tio1 = serial_tx
tio2 = serial_rx
tio3 = high_z
tio4 = high_z
pdid = high_z
pdic = high_z
nrst = high_z
glitch_hp = False
glitch_lp = True
extclk_src = hs1
hs2 = None
target_pwr = True
tio_states = (1, 1, 1, 0)
cdc_settings = [1, 0, 0, 0]
aux_io_mcx = high_z
glitch_trig_mcx = trigger
glitch =
enabled = True
num_glitches = 1
clk_src = pll
mmcm_locked = True
width = 0
offset = 0
trigger_src = ext_continuous
arm_timing = after_scope
ext_offset = 0
repeat = 10
output = enable_only
phase_shift_steps = 1680
SAD =
threshold = 0
interval_threshold = 1
trigger_sample = 256
sad_reference_length = 256
emode = False
multiple_triggers = False
num_triggers_seen = 0
always_armed = False
ADS4128 =
mode = normal
low_speed = True
hi_perf = 2
LA =
present = True
enabled = False
clkgen_enabled = True
locked = False
clk_source = pll
trigger_source = glitch
oversampling_factor = 9
sampling_clock_frequency = 307104549.407959
downsample = 1
capture_group = glitch
capture_depth = 0
trace =
present = True
enabled = True
errors = False
trace_synced = True
trace_mode = parallel
trace_width = 4
clock =
fe_clock_alive = True
fe_clock_src = usb_clock
clkgen_enabled = True
fe_freq = 96000000.0
swo_clock_locked = False
swo_clock_freq = 307104549.407959
capture =
trigger_source = trace trigger, rule #0
use_husky_arm = True
raw = True
rules_enabled = [0]
rules = [{'rule': 0, 'patt': bytearray(b'\x00\x00\x00\x00\x00\x00\x00\x1a'), 'mask': bytearray(b'\x00\x00\x00\x00\x00\x00\x00\xff')}]
mode = off
count = 0
max_triggers = 1
triggers_generated = 0
record_syncs = True
matched_pattern_data = 0000000000000000
matched_pattern_counts = [0, 0, 0, 0, 0, 0, 0, 0]
XADC =
status = good
temp = 48.8 [C]
max_temp = 53.5 [C]
temp_trigger = 80.0 [C]
temp_reset = 59.9 [C]
ot_temp_trigger = 84.9 [C]
ot_temp_reset = 59.9 [C]
vccint = 1.011 [V]
vccaux = 1.793 [V]
vccbram = 1.014 [V]
userio =
mode = trace
direction = 3
clock_enabled = 0
clocks = Lister([None])
clock_source = usb
clocks_locked = True
drive_data = 0
status = 508
Individual pins =
D0 = TMS , output, status = 0, clock_enabled = 0, drive = 0, clock not supported
D1 = TCK , output, status = 0, clock_enabled = 0, drive = 0, clock not supported
D2 = TDO/SWO , input, status = 1, clock_enabled = 0, drive = 0, clock not supported
D3 = unused , input, status = 1, clock_enabled = 0, drive = 0, clock not supported
D4 = TRACEDATA[0], input, status = 1, clock_enabled = 0, drive = 0, clock not supported
D5 = TRACEDATA[1], input, status = 1, clock_enabled = 0, drive = 0, clock not supported
D6 = TRACEDATA[2], input, status = 1, clock_enabled = 0, drive = 0, clock not supported
D7 = TRACEDATA[3], input, status = 1, clock_enabled = 0, drive = 0, clock not supported
CK = TRACECLOCK , input, status = 1, clock_enabled = 0, drive = 0, clock not set
bitbanger =
data_pin = disabled
clock_pin = disabled
max_length = 512
max_record = 32
clk_div = 2
drive_edge = rising
check_edge = falling
inactive_state = high_z
inactive_data = 0
continuous_clk = 0
num_bits = 0
glitch_mode = drive_low
LEDs =
setting = 0 (default, as labelled)
errors =
sam_errors = False
sam_led_setting = Default
XADC errors = False
ADC errors = False
extclk error = False
trace errors = False
I’ve been printing out the fe_freq out because it seems to vary and move around quite a bit.
Am I missing something or is there something wrong with my setup?