–>hello I bought Electromagnetic Probes, preamplifier and openadc.
only want to use it to acquire data, but so far have not get data (output openadc).
How could check if ahy output data OpenADC. [Not use the trigger, to be used ?.]
–>which is the minimum signal frequency that can be stored. I have a signal of 250 kHz, it is able to acquire the signal or there is a problem?
–>I have an FPGA Xilinx 3e, but my FPGA presents no input signal.
–>I have an FPGA Xilinx 3e, but my FPGA is not input bits, output open adc, as I can actually get the 10-bit output openadc?
–>the input signal is Electromagnetic Probes —> + -800mv 250kHz, I just want to get the digitized data to the FPGA, but I can not obtner binary data 3E FPGA XILINX, as I test if the ADC9215 digitizing.
I find the reason for using the trigger?
Hello,
Are you using the example project? It was built for a 3E device at one point, so should be usable. I can’t give a lot of support since it’s basically part of your FPGA design!
If you aren’t seeing data out of it, the first thing to check is the output clock is working. Besides that check the LNA settings are OK if using the LNA.
All of the OpenADCs do get functionally tested, so the hardware itself should be ok!
Warm Regards,
-Colin O’Flynn
FPGA code is made in VHDL (attached code), the code is easy it is to capture and store the data, but can not store any data because it ahy digital to save data.
We do not use LNA, use the transformer input, do not use the AD8331, the trigger does not use.
I want to know the minimum and maximum values (voltage and frequency) that I can enter at each of the inputs (LNA and transformer).
My sign is (+ -800mv to 1 Mhz frequency maxima) let me know if you need to use the preamplifier or Openadc card is sufficient.
clock frequency of FPGA and card Openadc is 30 MHZ.
I just want to acquire data of 1 MHz is why buy “Open ADC” and preamplifier. not use the external CLK.
CODE XILINX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity hackert is
port( clk: in STD_LOGIC;
trigger: in STD_LOGIC;
adc_data:in STD_LOGIC_VECTOR(9 downto 0);
adc_or: in STD_LOGIC;
adc_clk : out STD_LOGIC
);
end hackert;
architecture Behavioral of hackert is
–signal count1 : integer range 0 to 500: =1;
signal count1 : STD_LOGIC_VECTOR(9 downto 0);
signal clk1: std_logic;
signal o: std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if (conv_integer(count1) < 250) then
clk1 <= ‘1’;
count1 <= count1 + 1;
elsif (conv_integer(count1) < 500) then
clk1 <= ‘0’;
count1 <= count1 + 1;
elsif (conv_integer(count1) = 500) then
clk1 <= ‘1’;
count1 <= “1111111111” ;
end if;
end if;
end process;
process(clk1)
variable store: std_logic_vector(9 downto 0);
begin
store(0):= adc_data(0);
store(1):= adc_data(1);
store(2):= adc_data(2);
store(3):= adc_data(3);
store(4):= adc_data(4);
store(5):= adc_data(5);
store(6):= adc_data(6);
store(7):= adc_data(7);
store(8):= adc_data(8);
store(9):= adc_data(9);
if(clk1= '1' and clk1'event) then
if(store(9 downto 0)<"0011011001" and store(9 downto 0)>"100000000") then
o <= clk1;
else
o <='0';
end if;
end if;
end process;
adc_clk<= clk1;
end Behavioral;
Have you confirmed the clock is getting to the OpenADC? The signal levels you describe sounds reasonable for the transformer input. The clock generation logic might give you trouble, I’d look into using a DCM block instead. But either way double-check with a scope you are getting the expected ADC clock first!
Friend, I want to do is acquire data from a non-stationary signal frequency 20 kHz to 20 MHz (+ - 400mV) I bought the preamflificador and OPENADC card.
which it is the minimum frequency and minimum voltage that can enter through the preamplifier and / or OpenADC.
I wish only acquire data from a non-stationary signal.
I just want the data I acquired analog signal to digital via USB using Python.
you will have the code for SPARTA3E card? Only to perform this task.
Python also wish to save the data signal.
the aim of my project is different from yours, I just want to acquire frequency and voltage signals above …
VERILOG not understand, I prefer VHDL, you will have a code where I can help my project ?.
Data can be stored low frequency (KHZ) ?.
It is possible to amplify the low frequency signal (KHZ) with preamplifier?
please answer me these inquetudes, thanks.
