Issue with Clock Output Configuration on CW305

Embedded Security ChipWhisperer Hardware
1

Hello,
I recently attempt to use the CW305 board with an oscilloscope. To achieve clock synchronization, I want to output the clock signal from the PLL on CW305 to the oscilloscope, so I connect the X6 port to the oscilloscope. Since I’m using PLL1 in the FPGA, I configure the settings as follows. However, I encounter an issue and would appreciate your assistance.

target.vccint_set(1.0)  
target.pll.pll_enable_set(True)  
target.pll.pll_outenable_set(False, 0)  
target.pll.pll_outenable_set(True, 1)  
target.pll.pll_outenable_set(False, 2)  
target.pll.pll_outfreq_set(10E6, 1)  

target.pll.pll_outsource_set('PLL1', 0)

Unfortunately, I observe no clock signal on the oscilloscope screen – only a flat line. The output only appeared when I enabled PLL0 (target.pll.pll_outenable_set(True, 0)). It seems the pll_outsource_set command is not functioning as expected.

Best regards,
Li

2

Hi,

Yup, you’re correct, those commands are referring to the output, not the PLL. I’ll get that fixed up, thanks for reporting this.

Alex

3

Hi Alex,
Thank you for your reply. I noticed the commit records on GitHub, but I think there might be a misunderstanding regarding my issue.
According to the documentation for pll_outsource_set(source, outnum):“Output 0 can be configured for PLL0, PLL1, or PLL2”, and “channel 0 connects to CLK-SMA X6”.
My question is: Why does the command pll_outsource_set('PLL1', 0) fail to route the PLL1 clock signal to SMA X6? Looking forward to your clarification.
Best regards,
Li

4

Are you having issues with routing? In your original post, you said that you need to run pll_outenable_set(True, 0) to get an output on that pin. This is expected, as that command controls whether or not the output pin is enabled, not whether or not the PLL is enabled. Is there any other indication that the routing is wrong?

5

Hi Alex,
After re-evaluating the configuration, I would like to confirm whether the following understanding is correct:
1.Using pll_outsource_set('PLL1', 0), I have routed the PLL1 clock signal to output 0
2.Using pll_outenable_set(True, 0) allow both output 0 and output 1 to simultaneously ouput the PLL1 clock signal
However, I observed increased noise levels in the power traces after enabling output 0. Is this expected behavior?
Looking forward to your guidance.
Best regards,
Li

6

Yup, that’s correct.

No, this call just enables output 0.

Yeah, this is expected.

7

Hi Alex,
Thank you very much. In my experimental setup, I need to use output1, so I believe output1 is already enabled. Then we only need to discuss whether output0 should be enabled. I have no further questions. Thanks again for your support.
Best regards,
Li

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