I have issues to understand the difference between clock frequency and sampling frequency on CWLITE? and what is their relationship with adc.decimate?
How can I change them ?
My clock setting looks like this
The clock for that configuration on the CWLite works as follows:
- The ChipWhisperer generates an internal clock (typically 7.37MHz, but there’s a lot of flexibility) from an internal clock using the CLKGEN DCM
- This clock is then sent to the target to clock it as well
- From this 7.37MHz clock, the ADC DCM generates a clock for the ADC. This is typically x4 of the CLKGEN frequency and determines the sample rate. There’s much less flexibility here. If we’re using the internal clock, we’re limited to either x1 or x4 of the target clock.
This link between the ChipWhisperer sample rate and the target clock is a key feature of ChipWhisperer and makes side channel attacks much more effective than they otherwise would be.
ADC decimation just tells the ChipWhisperer to keep only one in every X samples. Therefore, if
adc.decimate = 10, it will record only 1 in 10 samples, effectively cutting the sample rate by 10.
Does it mean, if adc.decimate =1, we will sample one sample each clock cycle? (in case we set CLKGen to x1) ?
Nope, it’s based on the ADC clock, so it will still be clkgen_x4. Setting decimate to 4 will be similar to clkgen_x1 (though not exactly because the sample being kept doesn’t line up with the trigger, so there will be jitter).