Hi.

It is very interesting to hear if someone tried to run a single cycle AES implementation on an FPGA…

This is not about the pipelined implementation but about the real single cycle implementation **when all 10 rounds run during one clock cycle.**

I guess the main problems of such implementation are:

- There must be used only combinational logic.
- Propagation delay.

Probably, both problems are in theory resolvable. Say, by using the Kintex-7 FPGA and 1 Mhz external clock. This should be enough to have suitable propagation delay and hence to get rid of the sequential logic for storing intermediate round states.

As the main leakage of the hardware AES implementation is a Hamming distance between the cipher text (output of 10-th round) and the 9-th AES-128 round, using the suggested single clock cycle implementation will make impossible to apply the HD leakage model due to absence of the sequential logic (flip-flops to store the round states).

What leakage model can be used in this case? Is it still possible apply the CPA attack against proposed implementation?