Loading an application to the programmed FPGA

I’m currently working on programming my FPGA using the ChipWhisperer CW305 board, and I’m trying to load an application onto the FPGA as described in the ibex-demo-system directory (link).

The demo system in the directory is tailored for the Arty-A7 board, but I’m adapting it for the CW305. I’ve successfully loaded a bitstream onto the FPGA using a Jupyter Notebook.

However, when attempting to load an application onto the FPGA using the following command:


./util/load_demo_system.sh run ./sw/c/build/demo/hello_world/demo ./util/cw-openocd-cfg.tcl

I encounter issues. I suspect the problem might be with the cw-openocd-cfg.tcl file, which I attempted to configure based on the arty-a7-openocd-cfg.tcl file from the ibex-demo-system.

Open On-Chip Debugger 0.11.0
Licensed under GNU GPL v2
For bug reports, read
OpenOCD: Bug Reporting
Info : clock speed 500 kHz
Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway…
Error: riscv.cpu: IR capture error; saw 0x00 not 0x01
Warn : Bypassing JTAG setup events due to errors
Error: dtmcontrol is 0. Check JTAG connectivity/board power.
Warn : target riscv.cpu examination failed
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
none separate

Error: Target not examined yet

Can anyone provide assistance or guidance on how to correctly configure the cw-openocd-cfg.tcl file for use with the ChipWhisperer CW305 board? Feel free to ask if you need more details about my setup or if further clarification is required. Any help would be greatly appreciated!

cw-openocd-cfg.tlc content:

ChipWhisperer MPSSE

adapter driver ftdi
transport select jtag

The pid needs to be specified and depedends on

hardware in use. ChipWhisperer-Lite = 0xace2 for example.

ftdi_vid_pid 0x2b3e 0xace2

If you get an error about ‘ftdi’ being an

unknown command, change them to use an

underscore between ‘ftdi’ and the parameter. e.g.:

#ftdi_channel 1

ftdi_channel 1
ftdi_layout_init 0x001B 0x001B

reset_config none

Configure JTAG chain and the target processor

set _CHIPNAME riscv

Ibex Demo System JTAG IDCODE

set _EXPECTED_ID 0x11001CDF

jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_EXPECTED_ID -ignore-version
target create $_TARGETNAME riscv -chain-position $_TARGETNAME

ftdi_layout_signal nSRST -data 0x0010

ftdi_layout_signal SWD_EN -data 0x0100
ftdi_layout_signal SWDIO_OE -data 0x0200
adapter speed 500

riscv set_prefer_sba on

reset_config none



reset_config srst_push_pull

There should be no need to adapt anything for the CW305: there is already support for the CW305 (see e.g. the synth_cw305 target in ibex_demo_system.core). It should just build, out of the box.

For programming firmware, you’ll need an external JTAG programmer connected to the “FPGA JTAG” header (lower left corner of the CW305).

I’ve done this successfully using Tigard and this openocd config file:

interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 1
adapter_khz 500 
ftdi_layout_init 0x0038 0x003b
ftdi_layout_signal nTRST -data 0x0010
ftdi_layout_signal nSRST -data 0x0020
transport select jtag

# Configure JTAG chain and the target processor
set _CHIPNAME riscv

# Configure JTAG expected ID: choose the correct device!
# xc7a100t:
set _EXPECTED_ID 0x0362D093
# xc7a35t:
#set _EXPECTED_ID 0x13631093

jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID -ignore-version
target create $_TARGETNAME riscv -chain-position $_TARGETNAME

riscv set_ir idcode 0x09
riscv set_ir dtmcs 0x22
riscv set_ir dmi 0x23

riscv set_prefer_sba on
gdb_report_data_abort enable
gdb_report_register_access_error enable
gdb_breakpoint_override hard

reset_config none


Also, in case you haven’t noticed, there are also some CW-style SimpleSerial applications (ibex-demo-system/sw/c/demo/simpleserial-aes at main · lowRISC/ibex-demo-system · GitHub)

Thanks a lot. I will give it a try and give you a feedback

Hello everyone,

I don’t have an external JTAG programmer at the moment. I’ve heard that it might be possible to use the ChipWhisperer 20-pin connector and connect the necessary pins to the FPGA JTAG header instead.

Could someone please confirm if this is possible, and if so, could you provide guidance on which pins on the JTAG header should be connected?

I apologize if this question seems basic, but I’m relatively new to this field and still learning. Any help or advice would be greatly appreciated!

Thank you in advance.

The debugging capabilities of the ChipWhisperer is just a software implementation of MPSSE, so it might not work great with some chips. What capture board are you using?