Loading testacase data to victim design in CW305

I would like to download some test code to my design ( contains cpu and memories) which is now inside the FPGA in CW305.
Basically in my design the code is downloaded via JTAG.

Can I utilise the CW305 custom USB interface functionality
“writing onto data-bus for FPGA” or how should I do it?

Is there documentation available about this custom USB interface?

Regards, Sirpa Korhonen

FPGA memories can be initialized in the bitfile itself. We do this with our ARM DesignStart example.

It should also be easy to add a bridge to your internal CPU memories via the SAM3U USB interface.

See section 8 of https://www.newae.com/post/whitepaper-cw305.

Otherwise, if you have a CPU inside your FPGA design, you may find it easy to use the UART interface to pass data back/forth, just like all our non-FPGA target CPU examples do (and the ARM DesignStart example too).