Map a design to CW305

I’m trying to use the ChipWhisperer with CW305-FPGA target board to collect power traces of a design.
I’d like to know if there is a way to modify the input/output ports.
The design that I’m working on recieves the plaintext in two seperate shares(https://github.com/Chair-for-Security-Engineering/NullFresh/tree/master/HDL%20Ciphers/AES/Without%20Key%20Masking).
so I’d like to know how I can modify the ports of the cw305_top.v to read the plaintext with two shares.

Have a look at this to learn more about what you can do with the CW305:

There are lots of possible ways to communicate with the CW305 target. Our reference design uses a simple register map; you can easily extend that to add registers that the host can read/write to set up the shares.

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Thank you for your answer. I’m gonna try it :slight_smile: