Hello
I have cwPro ( 1200)
using clock_src = clkgen
and clkgen_src = system
and adc_src = clkgen_x1
for glitch module i was able to generate clkgen_freq = 250 MHZ
and clkgen dcm lock ok , but adc not
the max possible freq that can lock both dcms was 172 MHZ
is there some config to reach a higher ADC clock ?
tnx
Hi,
The max sampling frequency of the CW1200 is 105MS/s, so we don’t guarantee that anything works above 105MHz.
Alex
tnx Alex
so better i use ~100 MHZ max for both ADC and Glitch
So is 105 MS/s an arbitrary limit?
Because like @mxchip I was also able to go way beyond 105 MS/s.
On the CWLite I could set the clkgen_freq to up to 167.7 MHz with the ADC locking.
Not arbitrary at all. The ADC is rated to 105 MSps, and the FPGA bitfile is implemented to allow a maximum clock of 105 MHz.
Things don’t suddenly break at 106 MHz, but 105 is the max where they are guaranteed to work. Also keep in mind that even if things appear to work at a higher clock, taking components like the ADC out of spec means that their performance can degrade.