Maximum clock frequency for VCC glitching?

Hello everyone,
I have a CW1200 and I’m trying to do Voltage Glitching with it.
I’m aware that the CW1200 has 2 DCMs, one for the ADC module and another one that is used by the Glitch module of the CW.

I’m trying to understand what is the maximum clock frequency that the DCM used by the Glitch module can be set to, as I would like to know what is the maximum granularity that can be achieved in terms of the glitch length (considering glitch.output=‘enable_only’ and the use of glitch.repeat).

I have set:
scope.glitch.clk_src = ‘clkgen’
scope.clock.clkgen_freq = 320e6

Even though the ADC DCM is not LOCKED, I observe that the DCM used for glitching is LOCKED, and therefore I’m assuming it is possible to produce voltage glitches using this clkgen_freq. Am I correct here or am I misunderstanding something? If this is possible, is it as reliable as having for example clkgen_freq set to 100MHz (where even the ADC DCM is LOCKED).
For some reason, in my CW1200, when I set glitch.repeat to, for example, 50 or 100, the ‘Glitch Trig’d’ LED stays ON after the glitch is triggered, even-though, in the oscilloscope I observe that the glitch has already stopped, this doesn’t look like expected behavior. For glitch.repeat=1 I don’t observe this behavior.

Then I also have 3 extra questions:

  1. When we enable both glitch_hp and glitch_lp mosfets, are they indeed both being used for glitching or should I only use either one of them?
  2. I’m not understanding what exactly am I supposed to observe on pin HS2, after having it set to ‘glitch’. A clock signal?
  3. Is it normal that having the CW1200 inserted into the power line where I’m glitching causes the voltage on that line to oscillate or is this oscillating behavior normal on a power line?

Thank you a lot for all the clarifications!

There is a difference generating a clock, and having the scope use that clock. Our capture hardware can generate clocks that are faster than what they can use themselves. On CW1200 and CW-lite, our specs state that the clock generation range is 5-200 MHz. In practice you may be able to go higher; that will be limited by the DCM’s limit, but also other things such as PCB layout.

Now separately from that, any FPGA logic which uses this clock is only rated up to 105 MHz. This includes ADC sampling and glitch generation. Your CW1200 may work beyond that but it may not work reliably.

You may just need to “kick it” to force it to relock with scope.clock.reset_adc() (or, as per above, it may simply not lock reliably above 200 MHz).

No, as per above, going over 105 MHz may not be reliable.

Is the glitch source clock > 105 MHz in this scenario? If so this is the sort of behaviour you risk seeing when you go out-of-spec.

Yes, they’re both used.

If you go through our fault101 clock glitching notebooks, you’ll learn how to generate a glitchy clock on HS2.


Hey @jpthibault,
Thank you for answering all the questions, they clarified a lot!