Measure trigger length

1

Hello
is it possible to measure trigger length in clock cycles ( based on CW glitch clock freq)
for example using oscilloscope i measure toggle trigger pin ( ON-OFF) and is around 520 ns
the target device elapsed time of crypto func is around 700 ns and on in oscilloscope is 9000 ns
so i believe i need 2 things
1- add extra nops after set trigger high to allow CW receive trigger signal before or at or after crypto core receive start signal (in just few clocks )
2-need find aprox trigger length based on CW clk freq , to set ext_offset in more logic way.
tnx for any help

2

scope.adc.trig_count will tell you how many clock cycles the trigger was high, in ADC clock cycles.

3

tnx , but seems trig_count is a sum of duration ( old+current) right ?

4

It’s reset before every capture, but if you’re using a Lite or Pro with older firmware the reset doesn’t always take.
This should be fixed in 5.6.1 onwards.

5

tnx again , m using 5.6.1 , and seems it include the reset in verilog module

always @(posedge adc_clk)
if (trigger == trigger_level_i) begin
trigger_length <= trigger_length + 32’d1;
end else if(arm_i & ~arm_i_dly) begin
trigger_length <= 0;
end

i think better use ur patch in python
for example left value is trig_count - previous , right is trig_count
513912 14781599
513971 513971
513957 513957
509171 509171
478573 478573
513931 1027895
487830 487830
513963 513963
as u see ur python suggestion is more stable

scope.arm() // normaly fpga should zero trigger_length
initial_trig_count = scope.adc.trig_count
…
…
ret = scope.capture()
curr = scope.adc.trig_count
actual_trig_count = curr - initial_trig_count

6

I thought it did, but It’s possible the fix didn’t go into that build.
I know the develop branch definitely has the fix. Alternatively, use the workaround that’s mentioned in the github issue that I linked above.

7

yup , seems github branches such 5.6.1 …etc are outdated or non updated verilog project , since some inputs not related to some modules ( not possible to build bit file without some modification)
so i think better focus on develop branch