I am new to Chip Whisperer. I am wondering how to start a project that will measure power traces on a simple combinational circuit such as ISCAS85 c17. My first objective is to configure the target board to contain the logic of this benchmark. Thanks
Yup, it should be possible if I understand your situation correctly (combinational circuit running in an FPGA). Basically, you’ll need to route a trigger pin out of the FPGA that the chipwhisperer can use to start the capture. If you’re not using a ChipWhisperer target board, you’ll also need to make some hardware modifications to enable the ChipWhisperer to measure power consumption.
It’s important to understand that the ChipWhisperer will only be useful for measuring AC power consumption and not for measuring the base power consumption of your circuit.
Thank you, that makes sense. I found some tutorials on how to capture power consumption, but how would I configure the FPGA to hold a specific combinational circuit?
I have a ChipWhisperer-Lite (2-Part Version) with an XMEGA target
Oh, if you only have a Lite/Xmega, you won’t be able to load stuff you want to measure the power consumption of onto the FPGA. You need a separate FPGA target (like the S6LX9 target or the CW305).
How would I be able to do this with a CW308? Thank you.
As mentioned above, you need the S6LX9 target board. We provide some verilog source for implementing serial communication and a Xilinx ISE project: https://github.com/newaetech/chipwhisperer/tree/develop/hardware/victims/cw308_ufo_target/spartan6lx9
It wouldn’t be possible to do this on STM32F right? Thanks Alex.
I think some microcontrollers include modules for glue logic, but I’m not sure that would even be discernible on a power trace (though I’m not sure it’ll be visible on an FPGA either)
I was able to get my hands on a CW305 Artix 7 FPGA target. However, I am still confused on how load a new design onto the FPGA. I tried looking at a Vivado project in one of the tutorials, but it doesn’t explain how to start a project like this from scratch. Could you guide me in the right direction? Thanks
To start a new Vivado project, use our reference AES project as an example which shows how you can communicate with the FPGA target. More details are given here (section 8):
So based on the reference AES project, aes_core.v is the encryption logic that I should replace with my own design? Then cw305_top.v needs to be modified to connect to the new module? Do I need to change the register or clock files at all?
Yes, aes_core.v contains the AES encryption logic.
Change the register and clock modules as you wish, however your requirements dictate! The reference example is just an example, and if you look at CW305.py, then you’ll see how you can read/write the registers in registers.v from Python. These can be whatever you want.
Is it possible to program the CW305 FPGA with the Jupyter/Python ChipWhisperer libraries? I cannot get my board to connect to Vivado, which is on a virtual server.
target = cw.target(scope, cw.targets.CW305, bsfile='your_bitfile.bit', force=True)
How do you set up the trigger to capture data? I got an error in Jupyter for: Timeout in OpenADC capture(), no trigger seen, trigger forced, data is invalid
A zero-to-one transition on the IO4 line (on the 20-pin connector) is what initiates the trace capture. Your target FPGA needs to drive this line.
Read through section 5 of the whitepaper I mentioned previously for more details: