Min/Max Possible Frequencies of CLK Gen HS2


#1

Hello All.

I have looked through the wiki, source code, and forum and I have not been able to find an answer to this question.

Does anyone know what the clock generator (FPGA-HS2 ) frequency limits are? I was trying to produce a clock of 1 MHz and it didn’t seem like it was possible. Does anyone know the possible min and max frequencies that the ChipWhisperper Lite can produce?

Thanks in advance for your time and help.


#2

Ah, the old CW4 GUI made this more clear:


#3

Ah. So it appears like the slowest frequency that the CWLite can output is 5 MHz. Darn.

Thanks for finding that information!