Multiple physical resets required for output else garbage output


While working with CW305, I had to run numerous iterations with my bit file to see the final output once correctly. I know the bitfile (and the code) is correct, having tested it on simulations and using the SAKURA-G board (so no doubts, and hence questions on that).

The sequence of steps I needed to do to arrive at the correct output are as follows:

  1. From the previous run, run scope.dis()
  2. Restart and clear all kernel outputs.
  3. Power cycle the CW305
  4. Import chipwhisperer cw() and my functions for instance, cw_myFunction()
  5. Proceed to subsequent steps (configuration, test bector input and output viewing)
  6. If I need to run a subsequent script in the same notebook which requires giving another input, I have to do 1-5 else I end up with garbage output.

Is this expected or am I missing something here?
Let me know if further info is needed.

This points to some implementation issue. Any number of things can go wrong; for example you could have some issue related to clocks. Simulation is often not 100% equivalent to the live hardware. With regards to Sakura-G: my understanding is that it uses a Spartan-6 device, which is very different from the Artix-7 on the CW305. There is certainly potential for things to go wrong when porting a design from one FPGA family to another.

My next step would be to instantiate ILAs, or route internal signals to pins on a header, to debug what’s going on.