First, I implemented “PA_HW_CW305_1-Attacking_AES_on_an_FPGA” demo, and I recovered subkeys successfully. Next, I read the whitepaper, implemented " Tutorial CW305-1 Building a Project", and recovered subkeys successfully. Now I want to make a subtle change to aes_core.v or any other AES related verilog code, and observe plotted traces and recovered subkeys as part of learning the capabilities of CW products.
Therefore, I tried to change something in aes_core.v, but I got the encryption error as shown in the picture below. Every time I try to make subtle changes to verilog blocks(aes_core.v, aes_ks.v, or even cw305_reg_aes.v), I either get the error below, or I get the same result as the demo.
Is there a way that I can play around with the given AES to observe various traces and numbers of subkeys?
Target board: CW305-100T
Capture Box: CW1200