I’ve got the PW source from Github. After opening the pw_fpga project in Vivado v2020.2 (WebPACK edition, Linux), an updated version of the FIFO is generated (update from version 13.2 Rev 4 to 13.2 Rev 5).
My problem: the IP generator writes out an encrypted fifo_generator_0_sim_netlist.v, which cannot be used in Icarus Verilog.
How do I get an unencrypted post-synthesis netlist of the FIFO like the one in the PW source? I couldn’t find any possibility in Vivado.
I’ve search the Xilinx Forum, but without any result. Any hints or ideas?