I’ve got the PW source from Github. After opening the pw_fpga project in Vivado v2020.2 (WebPACK edition, Linux), an updated version of the FIFO is generated (update from version 13.2 Rev 4 to 13.2 Rev 5).
My problem: the IP generator writes out an encrypted fifo_generator_0_sim_netlist.v, which cannot be used in Icarus Verilog.
How do I get an unencrypted post-synthesis netlist of the FIFO like the one in the PW source? I couldn’t find any possibility in Vivado.
I’ve search the Xilinx Forum, but without any result. Any hints or ideas?
No, unfortunately – it looks like we were lucky that in earlier versions of Vivado, the FIFO simulation IP is not encrypted.
You could install Vivado 2019.1. Or, since the Xilinx changelogs say that there aren’t any functional changes in the FIFO generator between the 2019.1 and 2020.2 versions, just keep a copy of the 2019.1 files around for simulation?
Jean-Pierre
Hi Lars,
I have another project that I just migrated from 2019.2 to 2020.2, and in that case the FIFO remains unencrypted. The only difference as far as I can tell is that the FIFO generator did not change between those two versions, and so the upgrade process didn’t touch the simulation netlist. So I’m guessing that it’s the upgrade process which is turning on the Verilog encryption when going from 2019.1 to 2020.2.
The workaround then would be to re-create the FIFOs from scratch in 2020.2. I’ll do this when I get the chance, but I thought you’d like to know ASAP in case this is still blocking you.
Jean-Pierre