Programming Error: CW308T-S6LX9

Hello together,

I am new to the ChipWhisperer community and trying to set up the CW308T-S6LX9 target on my board.

I downloaded and installed iMPACT and connect to the board via a Xilinx Platform Cable.
However, the device ID returns 0000 1111 1111 1111 1111 1111 1111 1111 and I cannot program the board.

I measured the TDI/TDO and CLK with an oscilloscope:
CLK: Stable 3.3V
TDI: One edge to 0 when trying to read the device ID
TDO: No edges

The red LED on the FPGA is on as well as the different power supply level LEDs on the UFO board.

I do not fully get step (2) “Use settings as in the ‘Default XMEGA’ or ‘STM32Fx’ targets (i.e., clock jumpers, etc)” as I cannot find the settings for these boards either.

Highly appreciate any help!

Philipp

Connect the 20-pin cable between the CW308 and your ChipWhisperer capture device (CW-lite?).

On the CW308:

  • set the J3 jumper to HS2/OUT
  • set the J14 jumper on the two left-most pins
  • set the 1.2V and 3.3V LDO SRC switches to “J1/CW”

Double-check that you’ve connected your platform cable as shown here: CW308T-S6LX9 — ChipWhisperer Documentation

If this still fails, post a picture of your CW308, with all cables connected.

J-P

Thank you for the quick reply!
Yes, I have the CW-Lite Starter Kit + the CW308T-S6LX9 target.

Philipp

I can’t quite tell from the picture, is J3 set to HS2/OUT?

Have you run scope.default_setup()?

Remove the SMA cable, and what you’ve connected to the shunt header pins.

Yes, J3 is set to HS2/OUT and I removed the SMA cable as well as the connections to the shunt header pins.

scope.default_setup() returns:


scope.gain.mode          changed from low                    to high                     
scope.gain.gain          changed from 0                      to 30                       
scope.gain.db            changed from 5.5                    to 24.8359375               
scope.adc.basic_mode     changed from low                    to rising_edge              
scope.adc.samples        changed from 24400                  to 5000                     
scope.adc.trig_count     changed from 2403162637             to 2425229819               
scope.clock.adc_src      changed from clkgen_x1              to clkgen_x4                
scope.clock.adc_freq     changed from 96000000               to 29538471                 
scope.clock.adc_rate     changed from 96000000.0             to 29538471.0               
scope.clock.clkgen_div   changed from 1                      to 26                       
scope.clock.clkgen_freq  changed from 192000000.0            to 7384615.384615385        
scope.io.tio1            changed from serial_tx              to serial_rx                
scope.io.tio2            changed from serial_rx              to serial_tx                
scope.io.hs2             changed from None                   to clkgen                   
scope.io.tio_states      changed from (1, 0, 1, 0)           to (0, 1, 1, 0)             
scope.io.cdc_settings    changed from [1, 0, 0, 0]           to [0, 0, 0, 0]             

If I directly add the bitstream file as device the platform cable still returns the ID Code 0x0FFFFFFF.

If I run a boundary scan via “initialize chain” it does not find a device.

I tested the cable and iMPACT for a different board and could establish a connection.

I’m curious to see if you can connect to the FPGA on the CW-lite itself, to eliminate some variables.

You would need a header or some hook-up wire. No soldering necessary since this is just for a quick test.

The CW-lite FPGA’s JTAG port is labeled J4, near the top of the board and to the right of the USB connector on the image below.

Let me know if you’re unable to do this.

Hello,

trying to connect to the FPGA on the CW-Lite via JTAG also leads to an issue with the scan chain.

The successful boundary scan on a different board was with the ribbon cable from the platform cable directly.

For both, the CW-Lite FPGA and the CW308T-S6LX9, I used a custom adapter (connectivity and correct routing are double checked).

I can not use the custom adapter on the different board with the successful boundary scan yet because of the different size of the connectors. I am trying to find a solution.

I am suspecting the wire length of the current adapter as the platform cable documentation say that the flying wires adapter is not recommended.

“This method of connection is not recommended because it can result in poor signal integrity.”

Ok, we are getting closer!

I have no trouble with the “flying wire adapter cable” that is included with Xilinx’s platform cable USB II (see here: Platform Cable USB II )

The wires in this case are approximately 15cm long.

Have you tried reducing the JTAG clock rate?

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Thank you very much for your help!

I created a new connection with wires of around 10cm and it worked out.

great, happy to hear it!

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