Reason for error? WARNING:root:Timeout in OpenADC capture(), trigger FORCED

Hello. Does anyone know why I might be getting this error in Chipwhisperer 5 when trying to capture traces on my CW305 board?

WARNING:root:Timeout in OpenADC capture(), trigger FORCED
WARNING:root:Timeout in OpenADC capture(), trigger FORCED
/home/jackie/chipwhisperer5/software/chipwhisperer/ UserWarning: Timeout happened during capture
  warnings.warn("Timeout happened during capture")
Failed capture

This is only happening for new bitstreams that I am testing, where I am using a MMCM module to phase shift the clock. I have done very similar implementations in the past, and have tested them in Chipwhisperer 5 and do not get this error.

I have seen other posts where people have had this issue, but I am not sure if they are applicable to my board / situation. My setup works fine as long as I do not use these specific bistreams. I am using all of the default scope and target settings from the CW305 tutorial on juypyter notebooks. I get the same issue whether I use clkgen_x4 or extclk_x4 as my clock.

Is this warning always caused by issues with a clock? Do you think maybe my bitstreams are bad, or maybe there is some way to tweak the clock settings to get this to work?

This error means that your CW board didn’t see a trigger; in my experience it’s always indicative of a problem on the target side (e.g. the target isn’t issuing a trigger).

If you’re using a CW-lite then you can use a logic analyzer to look at what IO4 is doing, you can get to it easily on the 10-pin header that’s next to the 20-pin header.
Or instantiate an ILA in your design.


Thank you, that makes sense. I am pretty sure this issue is caused by my design, in which I am messing around with the clock using MMCM and PLLs. I think I just made a mistake when setting up the components, because when I run designs used Vivado’s Clocking Wizard to instantiate these components everything works fine. If this continues, I will definitely break out the logic analyzer or try using an ILA.

I just wanted to note that I continued to have this error from time to time, because I am modifying the clock used by AES in multiple ways. However, I found that you wrote a tutorial for clock glitching, which is similar to what I am working on, in which a reset_target(scope) method was used. This method is defined in chipwhisperer5 under jupyter/Helper_Scripts/Setup_Generic.ipynb. Using reset_target fixed this issue for me. Here is a link to the clock glitch attack:

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