Regarding the Details of the Default Bitfile’s SAD

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Hello,
I’ve recently become interested in the CW-Husky and started researching it, but there are still many parts I don’t fully understand.

I have a few questions regarding the details of the default bitfile’s SAD:

Q1. According to the README, does the default bitfile’s SAD refer to the esad module?

Q2. In chipwhisperer-husky-fpga/cwhusky.xpr, the value of INTERVAL_MATCHING is defined as 1. Does this mean that, when the default bitfile was built, the SAD was also in a state with INTERVAL_MATCHING enabled (set to 1)? Also, for the default bitfile, is the SAD actually operating in INTERVAL_MATCHING mode 1, or is it set to 0?

Q3. I’m also curious about the details of the SAD in version 5.7.0. In that version, was the default bitfile’s SAD based on the esad module, the sad module, or some other module? Additionally, in version 5.7.0, was the default bitfile’s INTERVAL_MATCHING mode also enabled (set to 1)?

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  1. Yes.
  2. Yes.
  3. If I remember correctly, we used sad_x2_slowclock.v. INTERVAL_MATCHING did not exist in 5.7. (the easiest way to determine that, since Verilog files were not tagged for older releases, is to look at the Python SAD API for the 5.7 release, which is tagged). The idea with the different SAD implementations is that they are all mostly functionally equivalent; we did different implementations to try to squeeze as many SAD samples as possible.
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