Use --sandbox_debug to see verbose messages from the sandbox and retain the sandbox build root for debugging
error[E0554]: #![feature] may not be used on the stable release channel
→ external/lowrisc_serde_annotate/serde_annotate/src/lib.rs:1:1
|
1 | #![feature(min_specialization)]
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
error: aborting due to previous error
For more information about this error, try rustc --explain E0554.
Aspect //rules:quality.bzl%modid_check_aspect of //hw/bitstream/vivado:fpga_cw340_test_rom up-to-date (nothing to build)
INFO: Elapsed time: 16.241s, Critical Path: 15.91s
INFO: 23 processes: 10 internal, 13 linux-sandbox.
FAILED: Build did NOT complete successfully
I am facing these issues when I am trying to run the following steps…
lmsm@lalit-HP-PC:~/FPGA_CW340/gitlab/5Jun2024/opentitan$ ./bazelisk.sh run //sw/host/opentitantool – bootstrap $(ci/scripts/target-location.sh //sw/device/examples/hello_world:hello_world_fpga_${BOARD})
INFO: Analyzed target //sw/host/opentitantool:opentitantool (0 packages loaded, 0 targets configured).
INFO: Found 1 target…
INFO: Elapsed time: 0.364s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
INFO: Build completed successfully, 1 total action
INFO: Running command line: bazel-bin/sw/host/opentitantool/opentitantool bootstrap /home/lmsm/.cache/bazel/_bazel_lmsm/9d1f72710d07cdf49a3547240d2914de/execroot/lowrisc_opentitan/bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/device/examples/hello_world/hello_world_fpga_cw340_fpga_cw340.bin
[2024-06-06T08:37:14Z WARN opentitantool] Could not read “/home/lmsm/.config/opentitantool/config”. Ignoring.
Error: Transport does not support Gpio
lmsm@lalit-HP-PC:~/FPGA_CW340/gitlab/5Jun2024/opentitan$ ./bazelisk.sh test --test_tag_filters=${BOARD} --test_output=streamed //sw/device/tests:uart_smoketest
WARNING: Streamed test output requested. All tests will be run locally, without sharding, one at a time
WARNING: All specified test targets were excluded by filters
DEBUG: /home/lmsm/FPGA_CW340/gitlab/5Jun2024/opentitan/rules/autogen.bzl:151:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
INFO: Analyzed 12 targets (31 packages loaded, 13440 targets configured).
INFO: Found 12 targets and 0 test targets…
INFO: From GenVivadoImage hw/bitstream/universal/splice-rom.update.mem:
2024-06-06 09:39:26,160 [gen_vivado_mem_image.py] Generating updatemem-compatible MEM file for ROM.
INFO: From SpliceBitstream hw/bitstream/universal/splice-rom.bit:
ERROR: [Bitstream 40-51] Unsupported part xcku095-ffva1156-1-c in bitfile external/bitstreams/cache/59ce6527192412790d566aaa633757aa4128a637/chip_earlgrey_cw340/lowrisc_systems_chip_earlgrey_cw340_0.1.bit.
****** updatemem v2021.1 (64-bit)
**** SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
**** IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /tools/Xilinx/Vivado/2021.1/scripts/updatemem/main.tcl -notrace
Command: update_mem -meminfo external/bitstreams/cache/59ce6527192412790d566aaa633757aa4128a637/chip_earlgrey_cw340/rom.mmi -data bazel-out/k8-fastbuild-ST-e4b88c99237c/bin/hw/bitstream/universal/splice-rom.update.mem -proc dummy -bit external/bitstreams/cache/59ce6527192412790d566aaa633757aa4128a637/chip_earlgrey_cw340/lowrisc_systems_chip_earlgrey_cw340_0.1.bit -out bazel-out/k8-fastbuild-ST-e4b88c99237c/bin/hw/bitstream/universal/splice-rom.bit -force
0 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
update_mem failed
ERROR: [Common 17-69] Command failed: Unable to read bit file ‘external/bitstreams/cache/59ce6527192412790d566aaa633757aa4128a637/chip_earlgrey_cw340/lowrisc_systems_chip_earlgrey_cw340_0.1.bit’ specified by the -bit switch.
INFO: [Common 17-206] Exiting updatemem at Thu Jun 6 09:39:30 2024…
ERROR: /home/lmsm/FPGA_CW340/gitlab/5Jun2024/opentitan/hw/bitstream/universal/BUILD:29:17: output ‘hw/bitstream/universal/splice-rom.bit’ was not created
ERROR: /home/lmsm/FPGA_CW340/gitlab/5Jun2024/opentitan/hw/bitstream/universal/BUILD:29:17: SpliceBitstream hw/bitstream/universal/splice-rom.bit failed: not all outputs were created or valid
INFO: Elapsed time: 119.759s, Critical Path: 72.99s
INFO: 112 processes: 42 internal, 67 linux-sandbox, 3 local.
FAILED: Build did NOT complete successfully
ERROR: No test targets were found, yet testing was requested
lmsm@lalit-HP-PC:~/FPGA_CW340/gitlab/5Jun2024/opentitan$
[ +0.108100] usb usb3-port4: attempt power cycle
[ +0.083901] usb 3-10.3.1: new high-speed USB device number 19 using xhci_hcd
[ +0.104844] usb 3-10.3.1: New USB device found, idVendor=2b3e, idProduct=c340, bcdDevice= 9.00
[ +0.000005] usb 3-10.3.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ +0.000002] usb 3-10.3.1: Product: ChipWhisperer CW340 - Luna Board
[ +0.000001] usb 3-10.3.1: Manufacturer: NewAE Technology Inc.
[ +0.000001] usb 3-10.3.1: SerialNumber:
[ +0.005438] cdc_acm 3-10.3.1:1.1: ttyACM0: USB ACM device
[ +0.000448] cdc_acm 3-10.3.1:1.3: ttyACM1: USB ACM device
[ +0.329241] usb 3-4: new full-speed USB device number 20 using xhci_hcd
[ +0.000130] usb 3-4: Device not responding to setup address.
[ +0.208217] usb 3-4: Device not responding to setup address.
[ +0.207643] usb 3-4: device not accepting address 20, error -71
[ +0.128017] usb 3-4: new full-speed USB device number 21 using xhci_hcd
[ +0.000145] usb 3-4: Device not responding to setup address.
[ +0.212043] usb 3-4: Device not responding to setup address.
[ +0.207901] usb 3-4: device not accepting address 21, error -71
[ +0.000128] usb usb3-port4: unable to enumerate USB device
[Jun 6 09:40] [UFW BLOCK] IN=wlp0s20f3 OUT= MAC=01:00:5e:00:00:01:94:98:8f:ee:80:b2:08:00 SRC=192.168.0.1 DST=224.0.0.1 LEN=36 TOS=0x00 PREC=0x00 TTL=1 ID=0 DF PROTO=2
[ +21.992052] [UFW BLOCK] IN=wlp0s20f3 OUT= MAC=a0:e7:0b:a9:e1:29:88:71:b1:aa:58:bb:08:00 SRC=192.168.0.10 DST=192.168.0.193 LEN=365 TOS=0x00 PREC=0x00 TTL=64 ID=60331 DF PROTO=UDP SPT=1900 DPT=50571 LEN=345