Tb.v and tb_cw305_reg_tasks.v simulation result

Embedded Security ChipWhisperer Software
1

Hi ,
I have tried to have the simulation result of tb.v, but I couldn’t make it. I used both VS Code & Icarus Verilog and Vivado 2019.1. Here are the error codes I have:

VS Code & Icarus Verilog:

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image848×597 15.2 KB

Vivado Design Suite 2019.1:

image

Please help. Thanks.

2

If you use the provided makefile, it will invoke iverilog with all of the required arguments.

VS Code and Vivado aren’t supported for simulation; only iverilog.