Timeout in OpenADC capture(), no trigger seen! Trigger forced

1

Hello,

I am trying to perform a Clock Glitching attack on the CW305 FPGA. ( same as the aes but i am using my own bit stream)
i know that to implement the bitstream i need the cw305 pll and for clock glitching i have to source the target clock from the capture hardware.
so the switcher configuration i am using is : J16=1 AND k16=0
those are the parameters configuration i am using

param
param1022×2024 180 KB

and i am having this error
errors
errors3034×110 32.8 KB

and this my trigger when i read it from the capture tio4 while doing the clock glitch
trigger
trigger2018×808 10.1 KB

2

I can’t tell what the problem could be from this. I would recommend starting with a non-glitchy clock, and use ILAs to see what your target is doing.

3

thank you for your answer.
i have an other question my target is running at 100MHz and the capture board insert the clock signal via hs2 at 10MHz should they be the same frequency or that is ok ?

4

I don’t understand the question but will take a guess at what you mean… you implemented your target with a clock defined as 100 MHz, now you will clock it at 10 MHz instead of 100 MHz, will it work?

I can’t answer that, it’s design-dependent (but generally speaking, yes that should be fine, unless you have a PLL which expects a 100 MHz clock and won’t be able to lock onto the 10x slower clock).