I have a question with regards to the CW305 Artix board and the tutorial NAEAN0010: Power Analysis on FPGA Implementation of AES Using CW305 & ChipWhisperer. On Section 5.2 Capturing Traces we use the function target.usb_trigger_toggle() for starting an encryption process.
When capturing traces, I obtain a pattern as the one shown below. The red trace at the bottom is the trigger and the blue trace is the power trace. During the triggering, we see 12 regions which (could) correspond to the AES rounds (?). Is my interpretation correct? Does this mean that the trigger signal goes down when the encryption process is finished?
If my interpretation is correct, why do we see 12 regions in the power trace? Aren’t we running an AES-128 which requires 10 rounds?
I count 11, not 12.
The reason it’s 11 instead of 10 is that the implementation uses a clock cycle for the initial round key addition. So if you refer to the steps here, when trigger goes high the target does:
step 2 (initial round key addition)
9 x step 3 (9 rounds)
step 4 (final round)
Each of these takes one cycle.
If you run the basic testbench we provide here, then you can see all this “in action”.
Great! Thanks a lot for the clarification. After the trigger signal goes down, there seems to be one last region which looks just like the regions corresponding to the rounds. But I guess since the trigger signal is already down, then it does not belong to the encryption process any more.
