Trying to change AES encryption for CW305 artrix fpga target

1

I have run the provided example of aes encryption in “jupyter/demos/PA_HW_CW305_1-Attacking_AES_on_an_FPGA.ipynb”. Here I see the bitfile being uploaded in following line

target = cw.target(scope, cw.targets.CW305, fpga_id=FPGA_ID, force=True)

The problem is I am not sure which bitfile is being uploaded as i don’t see any bitfile defined there. There might be default and i printed out the properties of target object which shows like below:

image
image2524×1531 305 KB

It shows a default verilog path which does not exist in my setup (I have downloaded the latest windows binary from github). But fpga seems running and the experiment shown here passes.

My question is, suppose I want to change something in the aes they provided and want to upload to the target board, how do i do that? also if i want to upload any other bitstream.

2

There are a few layers to it; the target object
pulls in the bitfile from here; the bitfile itself originates here.

If you have your own bitfile, you can program it to the FPGA using CW as follows:

import chipwhisperer as cw
scope = cw.scope()
target = cw.target(scope, cw.targets.CW305, bsfile=<path-to-bitfile>, force=True)
1 Like
3

Thank you so much. One more question, the way the setup is now, we can easily communicate with FPGA, sending key and texts. If i write my own bitfile, can you suggest a way that I can achieve that as well?

4

Have you seen our CW305 whitepaper? It will guide you towards understanding how everything works under the hood.

If you keep the same register interface that we use in the example AES target code, you can easily expand to read and write to arbitrary registers of your new design via the fpga_read() and fpga_write() methods provided by CW305.py.

5

thanks for sharing, I did not read the document before. Thanks for sharing