TVLA showing leakage on supposed secure implementation (ChipWhisperer-Lite / STM32F0)

1

Hi,
I’m running TVLA (fixed vs random t-test) on a supposedly leakage-free implementation for 100000 number of traces, but I still see significant t-test peaks (> ±4.5), even with ~100k traces.

Setup:

  • ChipWhisperer-Lite (CW308 STM32F0 / Cortex-M0)
  • TVLA: Welch t-test (fixed vs random)

What I observe:

  • Clear t-test peaks in multiple regions
  • Peaks persist even after increasing traces

My doubt: Not sure if this is:

  • real leakage in implementation, or
  • setup issue (trigger jitter, desync, UART issues, misalignment, etc.)

Questions:

  • Common TVLA pitfalls on CW308 STM32F0?
  • Best way to confirm the leakage is from the implementation or from setup issue?
  • Any known issues causing false t-test peaks?
  • Recommended sanity checks for ChipWhisperer TVLA setup?

For a closer look, I’ve attached here github link where the full code is there. I’m happy to provide any additional details if needed. Any insights or suggestions on debugging this kind of issue would be very helpful.
Link - GitHub - Satota17/TVLA-test · GitHub

2

It’s hard to give a full answer but my first wild guess would be that the implementation uses a masking scheme, which requires randomness, but you’re not using a good source of random data.

Whether or not the traces are aligned is something that you can (and should) easily check.

With regards to UART, make sure the traces don’t include the UART activity.

Also, read the literature on TVLA- it can be a useful tool but it is not a magic bullet.

Finally, it’s easy to claim that there is no leakage- have others verified that claim?

And one last thing- try running side-channel attacks!