Unstable target clock?

I am sampling a HCS301 chip. It probably has a simple RC oscillator - completely internal.
When sampling I can find a very distinctive max value (spike) which I have chosen as the start point.
I also find a very distinctive min value (also a spike) which I have chosen as the end point.
The length of the period between varies and I assume, but do not know, that it is partly related to a varying clock frequency.
The length of the interesting period in 16 traces were now:
12408, 12477, 12415, 12543, 12408, 12482, 12409, 12612,
12405, 12475, 12415, 12545, 12408, 12477, 12408, 12735

Only a small part of the differences seem to be related to a varying clock frequency. Anyway, is there a standard method for correcting the data?



If I understand this correctly you would like to resample (in software) to better align the traces. I don’t think this is a method that is often used but have a look at resampling/interpolation (in numpy).

Else pick the waveform that is the closed to the signal you are interested with to perform the alignment.

Hmmm, okay.

I first assumed the encryption was implemented in hardware, but then one encryption should take exactly 528 clocks. I know because I have done it with an FPGA. I am no longer sure my assumption is correct. If the encryption is done in software then the whole thing changes.

I think I need to study this more.


I think your suggestion is good (if I understood it correctly).
I will just sample until I get the traces I need with the length that I need.