Using a Custom C Algorithm on Husky

1

Hello!
I recently became interested in the CW-Husky and have started researching it, but there are still many parts I don’t fully understand.

This time, I would like to run a custom C algorithm on the CW-Husky. Similar to the provided SAD, the algorithm I want to implement is a pattern matching algorithm, and my goal is to run it at the hardware level.

Currently, I am using the CW-Husky, CW-308, and STM32F303.

What steps should I take to achieve this?

2

Hi,

Do you mean you want to write the implementation in C? If so, this won’t be possible as all the trace collection/trigger logic is implemented in the FPGA. All the microcontroller is really doing is facilitating communication between the FPGA and your PC, plus a few other things (UART, target programming, etc).

Alex

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3

Thank you for the explanation.
I was already somewhat aware that a C-based algorithm cannot be directly executed on the FPGA.

As far as I know, by converting C code into HLS code and then using Vivado to transform it into HDL and build it onto the FPGA, it is possible to run a custom algorithm at the hardware level. I am currently researching this approach, and as a first step, I would like to implement and run a custom pattern matching algorithm on the FPGA, similar to how SAD is executed on the FPGA. In this regard, I am wondering if there are any Husky-specific documents or guidelines available, as well as whether there is any practical know-how related to this process.

4

@jpthibault would be the person to ask about that, but he’s currently on vacation. There is the README at GitHub - newaetech/chipwhisperer-husky-fpga: FPGA design and test files for ChipWhisperer-Husky. which contains a lot of useful information regarding the Husky’s FPGA code. That repo of course contains the FPGA code as well. Hopefully that’s enough to get you started.

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5

Thank you. I have learned a lot thanks to your help.

Currently, as stated in newaetech/chipwhisperer-husky-fpga/README.md, I installed Vivado 2022.1 and am conducting research so that a user-defined pattern algorithm can run on the FPGA, similar to how SAD works on the FPGA. I loaded thecwhusky.xprfile in Vivado according to my Husky board and began practicing, but I could not find files specified with absolute paths such as C:/Users/user/Desktop/* and C:/home/jpnewae/git/*in the GitHub repository.

Are these files the ones referred to in the README statement:

“When opening the Husky or Husky Plus project, Vivado will report some ‘errors’ about missing IP that are not actually errors and can be safely ignored (these relate to ILA modules used in development which are not included in the repository, because they’re not used in the production bitfile).”

If not, where are these files provided?

Specifically, I am missing the following files:
trace_top.v, reg_trace.v, fe_capture_trace.v, fifo.v, fe_capture_main.v, reg_main.v, simple_trigger.v, uart_rx.v, fifo_generator_tiny, and cwhusky_top.dcp

6

Those are from submodules that you need to add. You’ll find them under the fpga directory.

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7

Oh dear, I missed this! Thanks for the reply.

8

Adding a bit more to this: documentation for the FPGA source code is light (it’s the README that you’ve seen). That is something I’d like to improve but for now, here’s how I suggest you approach this:

  • run simulations to help understand the FPGA code
  • to understand how the Python API layer talks to the FPGA, know that reads and write to FPGA registers look like this, and that the register names are identical in Python-land and in Verilog-land (e.g. that Python line writes to this register)
  • the Husky FPGA is very full now so it can be difficult to add more logic; the easiest way to manage this is to downsize some of the existing modules:
    • if you need more logic cells, the SAD module is by far the largest; either omit it or make it smaller by reducing pREF_SAMPLES; this is also useful even if you’re not adding much logic because it can make your Vivado runs much faster
    • if you need more BRAM, reduce the FIFO depths
  • once you have a bitfile, use the test script to ensure nothing is broken

Let us know if you have any specific questions; also let us know if what you’re working on is something you’d like to see merged into our codebase.

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