Violation building CW305 example project "aes128_verilog"

Embedded Security ChipWhisperer Hardware
1

Hello all,

I’m getting started with a CW305 and intended to start from the example project “aes128_verilog” on GitHub. I’m working with Vivado 2022.1.

I’m getting the following warnings in the methodology tab:

TIMING-6  
#1 The clocks tio_clkin and usb_clk are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks tio_clkin] -to [get_clocks usb_clk] 
#2 The clocks usb_clk and tio_clkin are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks usb_clk] -to [get_clocks tio_clkin] 

TIMING-7  
#1 The clocks tio_clkin and usb_clk are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks tio_clkin] -to [get_clocks usb_clk] 
#2 The clocks usb_clk and tio_clkin are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks usb_clk] -to [get_clocks tio_clkin]

Then, after P&R, I get the following timing violation:

From: U_reg_aes/O_clksettings_reg[3]/C (source clk: usb_clk)
To:   U_clocks/CWOUT_ODDR/CE (destination clk: tio_clkin)

I guess something’s missing in the constraints, at least with recent versions of Vivado.
I’m not sure what the relationship is between those two clocks and thus not able to figure out a fix.

Anybody faced this and can provide some guidance?

Thanks a lot!

2

I don’t have 2022.1 installed but adding this timing exception should clean that up:

set_clock_groups -asynchronous \
                 -group [get_clocks usb_clk ] \
                 -group [get_clocks tio_clkin]

There is no concern for timing between these clocks because all signals that traverse them are essentially static.
Jean-Pierre

3

Thanks a lot Jean-Pierre, that’s very helpful!