I am trying to sample my power trace off of a CW305 with a higher frequency than 4x the FPGA clock. Currently, I have my ADC connected to the external clock from the FPGA. I want to be able to increase my sampling frequency but if I rely on a different clock my synchronization is thrown off which is no good. Any links or resources to completed solutions to this problem would be great, but suggestions are welcome and helpful as well!
With the CW305 you have some options, but you’ll likely need Verilog modifications in any case.
you can use the CW305’s on-board CDCE906 PLL to generate all the clocks you need, sending the slower target clock to the FPGA and the faster sampling clock to your ChipWhisperer capture board via HS1 on the 20-pin connector.
you can send the FPGA the fast sampling clock and have the FPGA generate its own slower clock internally using a Xilinx MMCM or PLL primitive.
Unless your Verilog target’s design already accommodates one of these clocking scenarios, then yes you’ll need to make Verilog changes. Our AES example falls in that category.
Is the PLL2 clock assigned to the proper FPGA input pin? You need to uncomment this line in cw305_main.xdc: set_property PACKAGE_PIN E12 [get_ports pll_clk2]
Otherwise, check the log files for warnings.
You may also want to create an LED heartbeat signal for the new clock, like is done for the two existing clocks, in cw305_top.v, to get a visual indicator that the clocks are alive.
It seems the issue was something with my settings in Vivado, not sure exactly what it is but I imported the changes I made in a different project I have that is working, but the set_property for E12 was uncommented as well as the pll_clk2 in the inputs in cw305_top. It is now sampling at a higher frequency and the attacks are successful. Thank you very much for the help.