When to use LP or HP glitch configuration

Before connecting to real target / demo board, I want to understand very well how CWLITE work, so I’, analyzing with my scope signals of CW in various configuration. When I have a complete vision of the behaviors of the board I think I’m ready for real hand on.
Now my question, any suggest about when to use LP or HP configuration? If I understand the schematic both are used to put the SMA glitch line to GND, it’s right? For power glitch this has sense, but for clock? In clock glitch we can only affect the positive half wave of clock, because when clock is low glitch line can’t output an high level. In the documentation there is not (or I don’t have find it) a clear section that explain what pins to use in what scenarios. What I think is SMA port is only for power glitch and HS2 is for clock glitch.
In both case I think HS1 pin can be used to sync clock for power or clock glitch. Is LP + HP a right configuration to have more power? Clock glitch and power glitch can be used together?

Thanks!
GMG

Unfortunately there’s no one-size-fits-all answer here. There’s some discussion of LP vs HP in this paper: https://eprint.iacr.org/2016/810.pdf
and also in Colin’s Hardware Hacking Handbook (nostarch.com); basically LP tends to provide a faster response, so sharper and narrower glitches, but HP can provide better results for targets that have strong power supplies or decouping capacitors that can’t be removed. So, TL,DR: it depends on your target.

The LP/HP MOSFETs are not involved at all in clock glitching. With clock glitching, we just glitch the generated clock that’s output on the HS2 pin. Have a look at our fault101 clock glitching notebooks to see how this work (and, BTW, glitches can be generated anywhere in the clock period, in both the high and low phases).

Jean-Pierre