Hello everyone, thanks for a lot of help provided in the forum.
I am using a Chipwhister Lite to capture the signal. However, there are something I am really confused about:
The ADC of Chipwhisperer Lite is 105MS / s so its clock cycle is approximately 9.524 ns/sample. Also, it is 10-bit resolution, it takes 95.24 ns to acquire a sample. Is this correct?
I read this post, the answer of the post said the Chipwhisperer captures 4x faster than the target. Does the target capture the signal too ? I thought only Chipwhisperer’s ADC capture the trace.
When I was trying to capture the signal by get_last_trace in the default setting, it captures 5000 samples. For example, if the board capture 10000 samples, only the last 5000 are captured. Am I right? So if I want to capture the trace of whole process, I have to change the samples to 10000 ?
There are some DEBUG messages make me confused:
DEBUG:root:Trigger_data: [3 3 3 … 1 1 1] len=3064
DEBUG:root:Trigger found at 76
What is the “Trigger_data” ? Does that mean the samples from 0 to 3063 are all trigger data? But what about “Trigger found at 76” ?
Also, when debug message shows as following:
DEBUG:root:Processed data, ended up with 9116 samples total
DEBUG:root:Read 9000 datapoints
Does it mean the chipwhisperer captures 9116 samples but only the last 9000 is recorded ?
It’s more correct to say the max sample rate of the Lite is 105MS/s - depending on the ADC clock, this might be (and is for the default examples, which capture at 7.37MHz * 4) less. If you want to see the sample rate, you can check scope.clock.adc_freq. Bits here are just talking about the ADC resolution, with 10 bits meaning there can be 1024 possible values for each sample.
The ADC clock is usually based on the target clock as it greatly improve the quality of the data acquired. Typically, the ADC runs at 4x the speed of the target.
I’m not too familiar with how the data capture works on the FPGA, but I believe the capture starts when the ADC trigger is activated and ends once it has captured the requested number of samples. You can see how long the trigger is active for via scope.adc.trig_count.
Thanks for your clear explain! When I call scope.clock.adc_freq, the value is 29538459 . So it means it capture this much of samples in one second, correct?
So the maximum value I can set is: scope.clock.adc_freq = 105,000,000. Am I right?
Ok.
When I call scope.adc.trig_count, I got a value 23465065. Based on this value, I can approximate the time the board to capture the signal by scope.adc.trig_count / scope.clock.adc_freq , so the capture period is 0.2444 (23465065 / 96000000) . Am I right ? But what is the relation between scope.adc.samples and scope.adc.trig_coun ? I am still confused …
Do you mind to explain what the above message mean ? Thanks
Pretty much, except you can’t set scope.clock.adc_freq directly. To modify it, you have the modify scope.clock.clkgen_freq, which modifies the clock sent to the target, and scope.clock.adc_src, which changes the multiplier/source for the adc clock.
scope.adc.trig_count and scope.adc.samples are completely independent. The former is just how many adc clock cycles the trigger was high for and the latter is how many samples to capture.
Sorry, this is all data straight from the FPGA, which I don’t really know much about.
Besides, I found out the properties of the scope will change after I called cw.program_target(scope, prog, fw_path). For instance, before the function is call, the properties are:
After the function is done, the scope properties become scope.clock.adc_freq = 29538459 scope.adc.trig_count = 696
This will tell you how long the trigger is high for, not the capture period. Replace scope.adc.trig_count with scope.adc.samples to see how long the capture itself takes.
I can’t reproduce this. Are you calling anything else besides program_target()? If so, that’s likely what’s changing the adc frequency on you.
Thank you, but I am confused about the definition ofscope.adc.trig_count: “This value indicates how long the trigger was high or low last time a trace was captured”. What do high and low mean?
High is 3.3V and low is 0V. There is a pin on the target device that it sets to 3.3V when the desired operation starts and 0V when it ends (the trigger_high() and trigger_low() calls in the target firmware)
As for your code, scope.default_setup() sets scope.clock.clkgen_freq to 7.37MHz and the ADC clock to 4x the target clock, giving you your 29.5MHz adc freq.
I guess the quality of the screenshot is not good enough so you misread the code. Sorry for that.
The scope.clock.adc_freq is 127949157 after we call scope.default_setup(). The value only changes to 29.5MHz adc freq when we call cw.program_target(scope, prog, fw_path). It does not act as you say.
I’m guessing the adc clock didn’t have time to lock (or something along those lines) between you calling scope.default_setup() and scope.clock.adc_freq. As per its documentation, scope.default_setup() will always set the adc_freq to 29.5MHz.
