Again, the internal data path width is an implementation choices which is completely irrelevant to a functionally correct implementation.
Vivado (or any other synthesis tool) will remove any logic that is determined to not have any effect on top-level outputs. If you look at the synthesis log files, you will see messages indicating this. So it looks like your problem is a Verilog problem, not a CW305 problem.
If you can share your complete Verilog source code I can have a quick look to see if anything jumps out, but I can’t tell anything from those screenshots.
Jean-Pierre